Means To Reduce The PLL Phase Bump Caused By A Mis

专利名称：Means To Reduce The PLL Phase Bump

Caused By A Missing Clock Pulse

发明人：James Toner Sundby申请号：US11744420申请日：20070504

公开号：US20080273648A1公开日：20081106

专利附图：

摘要：A PLL includes control circuitry adapted to detect missing pulses of a referenceclock and to control an output voltage of a charge pump disposed in the PLL accordingly.A signal generated in response to the detection of a missing pulse is pulse-width limited

and applied to the charge pump during a first period. The detection of the pulse-widthlimited signal is used to generate a first slew signal that is also pulse-width limited andapplied to the charge pump during a second period. The detection of the first slew signalis used to generate a second slew signal that is also pulse-width limited and applied tothe charge pump during a third period. The amount of current supplied by the chargepump during the second charging period is equal to a sum of currents withdrawn by thecharge pump during the first and third time periods.

申请人：James Toner Sundby

地址：Tracy CA US

国籍：US

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