•Incorporates the ARM7TDMI® ARM® Thumb® Processor
–High-performance 32-bit RISC Architecture–High-density 16-bit Instruction Set–Leader in MIPS/Watt
–Embedded ICE In-circuit Emulation, Debug Communication Channel Support256 Kbytes of Internal High-speed Flash, Organized in 1024 Pages of 256 Bytes–Single Cycle Access at Up to 30 MHz in Worst Case Conditions
–Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed
–Page Programming Time: 4 ms, Including Page Auto-erase, Full Erase Time: 10 ms–10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash Security Bit
–Fast Flash Programming Interface for High Volume Production
64 Kbytes of Internal High-speed SRAM, Single-cycle Access at Maximum SpeedMemory Controller (MC)
–Embedded Flash Controller, Abort Status and Misalignment DetectionReset Controller (RSTC)
–Based on Power-on Reset and Low-power Factory-calibrated Brownout Detector–Provides External Reset Signal Shaping and Reset Source StatusClock Generator (CKGR)
–Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLLPower Management Controller (PMC)
–Software Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and Idle Mode
–Three Programmable External Clock SignalsAdvanced Interrupt Controller (AIC)
–Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
–Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
Debug Unit (DBGU)
–2-wire UART and Support for Debug Communication Channel interrupt, Programmable ICE Access PreventionPeriodic Interval Timer (PIT)
–20-bit Programmable Counter plus 12-bit Interval CounterWindowed Watchdog (WDT)
–12-bit key-protected Programmable Counter
–Provides Reset or Interrupt Signals to the System
–Counter May Be Stopped While the Processor is in Debug State or in Idle ModeReal-time Timer (RTT)
–32-bit Free-running Counter with Alarm–Runs Off the Internal RC Oscillator
One Parallel Input/Output Controller (PIOA)
–Thirty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os –Input Change Interrupt Capability on Each I/O Line
–Individually Programmable Open-drain, Pull-up Resistor and Synchronous OutputEleven Peripheral Data Controller (PDC) Channels
One USB 2.0 Full Speed (12 Mbits per second) Device Port
–On-chip Transceiver, 328-byte Configurable Integrated FIFOsOne Synchronous Serial Controller (SSC)
–Independent Clock and Frame Sync Signals for Each Receiver and Transmitter–I²S Analog Interface Support, Time Division Multiplex Support
–High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer Two Universal Synchronous/Asynchronous Receiver Transmitters (USART)–Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation
–Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support–Full Modem Line Support on USART1
One Master/Slave Serial Peripheral Interface (SPI)
–8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
•
•••••
AT91 ARM® Thumb®-based MicrocontrollersAT91SAM7S256SummaryPreliminary•
•••
••
•••
•
•
6117AS–ATARM–20-Oct-04Note: This is a summary document. A complete documentis not available at this time. For more information, pleasecontact your local Atmel sales office.
•One Three-channel 16-bit Timer/Counter (TC)••••••
–Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel–Double PWM Generation, Capture/Waveform Mode, Up/Down CapabilityOne Four-channel 16-bit PWM Controller (PWMC)One Two-wire Interface (TWI)
–Master Mode Support Only, All Two-wire Atmel EEPROMs Supported
One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/OsIEEE 1149.1 JTAG Boundary Scan on All Digital Pins
5V-tolerant I/Os, including Four High-current Drive I/O lines, Up to 16 mA EachPower Supplies
–Embedded 1.8V Regulator, Drawing up to 100 mA for the Core and External Components–3.3V VDDIO I/O Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply–1.8V VDDCORE Core Power Supply with Brownout Detector
Fully Static Operation: Up to 55 MHz at 1.65V and 85°C Worst Case ConditionsAvailable in a 64-lead LQFP Package
••
Description
Atmel’s AT91SAM7S256 is a member of a series of low pincount Flash microcontrollersbased on the 32-bit ARM RISC processor. It features a 256 Kbyte high-speed Flash anda 64 Kbyte SRAM, a large set of peripherals, including a USB 2.0 device, and a com-plete set of system functions minimizing the number of external components. Thedevice is an ideal migration path for 8-bit microcontroller users looking for additional per-formance and extended memory.
The embedded Flash memory can be programmed in-system via the JTAG-ICE inter-face or via a parallel interface on a production programmer prior to mounting. Built-inlock bits and a security bit protect the firmware from accidental overwrite and preservesits confidentiality.
The AT91SAM7S256 system controller includes a reset controller capable of managingthe power-on sequence of the microcontroller and the complete system. Correct deviceoperation can be monitored by a built-in brownout detector and a watchdog running offan integrated RC oscillator.
The AT91SAM7S256 is a general-purpose microcontroller. Its integrated USB Deviceport makes it an ideal device for peripheral applications requiring connectivity to a PC orcellular phone. Its aggressive price point and high level of integration pushes its scopeof use far into the cost-sensitive, high-volume consumer market.
2
AT91SAM7S256 Summary Preliminary
6117AS–ATARM–20-Oct-04
AT91SAM7S256 Summary Preliminary
Block Diagram
Figure 1. AT91SAM7S256 Block Diagram
TDITDOTMSJTAGICEARM7TDMI TCKSCANProcessorJTAGSEL1.8 VVDDINSystem ControllerVoltageGNDTSTRegulatorVDDOUTFIQAICVDDCOREIRQ0-IRQ1OVDDIOIMemory ControllerPEmbeddedSRAMPCK0-PCK2FlashAddress64 KbytesControllerDecoderPLLRCPLLXINPMCAbortXOUTOSCMisalignmentStatusDetectionVDDFLASHRCOSCFlash256 KbytesERASEVDDCOREBODPeripheral BridgeResetVDDCOREPORControllerPeripheral DataPGMRDYNRSTControllerFast Flash PGMNVALIDPGMNOE11 ChannelsProgramming PGMCKPITInterfacePGMM0-PGMM3PGMD0-PGMD15WDTAPBPGMNCMDPGMEN0-PGMEN1RTTDRXDODTXDIPDBGUPDCrePDCFIFOviUSB DeviceecDDMsnDDParPIOATPWM0RXD0PDCPWM1TXD0PWMCSCK0USART0PWM2PWM3RTS0CTS0PDCPDCTFTKRXD1PDCSSCTDTXD1RDSCK1RKRTS1CTS1USART1PDCORFIDCD1Timer CounterPTCLK0DSR1TCLK1DTR1TCLK2RI1OPDCTC0TIOA0ITIOB0NPCS0PPDCNPCS1TC1TIOA1NPCS2TIOB1NPCS3SPIMISOTC2TIOA2TIOB2MOSITWDSPCKPDCTWITWCKADTRGPDCAD0AD1AD2AD3ADCAD4AD5AD6AD7ADVREF6117AS–ATARM–20-Oct-04
3
Signal Description
Table 1. Signal Description List
Signal Name
Function
Power
VDDINVDDOUTVDDFLASHVDDIOVDDCOREVDDPLLGND
Voltage Regulator Power Supply Input Voltage Regulator OutputFlash Power SupplyI/O Lines Power SupplyCore Power SupplyPLLGround
PowerPowerPower PowerPowerPowerGround
Clocks, Oscillators and PLLs
XINXOUTPLLRCPCK0 - PCK2
Main Oscillator InputMain Oscillator OutputPLL Filter
Programmable Clock Output
InputOutputInputOutput
ICE and JTAG
TCKTDITDOTMSJTAGSEL
Test ClockTest Data InTest Data OutTest Mode SelectJTAG Selection
Flash Memory
ERASE
Flash and NVM Configuration Bits Erase Command
Reset/Test
NRSTTST
Microcontroller ResetTest Mode Select
Debug Unit
DRXDDTXD
Debug Receive DataDebug Transmit Data
AIC
IRQ0 - IRQ1FIQ
External Interrupt InputsFast Interrupt Input
InputInputInputOutputI/OInput
Low
Pull-Up resistorPull-down resistor
Input
High
Pull-down resistor
InputInputOutputInputInput
No pull-up resistorPull-down resistorNo pull-up resistorNo pull-up resistor3.0V to 3.6V1.85V nominal3.0V to 3.6V3.0V to 3.6V1.65V to 1.95V1.65V to 1.95V
Type
Active Level
Comments
4
AT91SAM7S256 Summary Preliminary
6117AS–ATARM–20-Oct-04
AT91SAM7S256 Summary Preliminary
Table 1. Signal Description List (Continued)
Signal Name
Function
PIO
PA0 - PA31
Parallel IO Controller A
USB Device Port
DDMDDP
USB Device Port Data - USB Device Port Data +
USART
SCK0 - SCK1TXD0 - TXD1RXD0 - RXD1 RTS0 - RTS1CTS0 - CTS1DCD1DTR1DSR1RI1
Serial ClockTransmit DataReceive DataRequest To SendClear To Send Data Carrier Detect Data Terminal ReadyData Set ReadyRing Indicator
I/OI/OInputOutputInputInputOutputInputInput
Synchronous Serial Controller
TDRDTKRKTFRF
Transmit DataReceive DataTransmit ClockReceive ClockTransmit Frame SyncReceive Frame Sync
Timer/Counter
TCLK0 - TCLK2TIOA0 - TIOA2TIOB0 - TIOB2
External Clock InputsI/O Line AI/O Line B
PWM Controller
PWM0 - PWM3
PWM Channels
SPI
MISOMOSISPCKNPCS0NPCS1-NPCS3
Master In Slave OutMaster Out Slave InSPI Serial Clock
SPI Peripheral Chip Select 0SPI Peripheral Chip Select 1 to 3
I/OI/OI/OI/OOutput
LowLow
OutputInputI/OI/OOutputInputI/OI/OI/OI/OAnalogAnalogI/O
Pulled-up input at reset
Type
Active Level
Comments
5
6117AS–ATARM–20-Oct-04
Table 1. Signal Description List (Continued)
Signal Name
Function
Type
Two-Wire Interface
TWDTWCK
Two-wire Serial Data Two-wire Serial Clock
I/OI/O
Analog-to-Digital Converter
AD0-AD3AD4-AD7ADTRGADVREF
Analog InputsAnalog InputsADC TriggerADC Reference
AnalogAnalogInputAnalog
Fast Flash Programming Interface
PGMEN0-PGMEN1PGMM0-PGMM3PGMD0-PGMD15PGMRDYPGMNVALIDPGMNOEPGMCKPGMNCMD
Programming EnablingProgramming ModeProgramming DataProgramming ReadyData DirectionProgramming ReadProgramming ClockProgramming Command
InputInputI/OOutputOutputInputInputInput
LowHighLowLow
Digital pulled-up inputs at resetAnalog Inputs
Active Level
Comments
6
AT91SAM7S256 Summary Preliminary
6117AS–ATARM–20-Oct-04
AT91SAM7S256 Summary Preliminary
Package and Pinout
The AT91SAM7S256 is available in a 64-lead LQFP package.
64-lead LQFP Mechanical Figure 2 shows the orientation of the 64-lead LQFP package. A detailed mechanical
description is given in the section Mechanical Characteristics of the full datasheet.Overview
Figure 2. 64-lead LQFP Package Pinout (Top View)
484933326411617Pinout
12345678910111213141516
ADVREFGNDAD4AD5AD6AD7VDDINVDDOUTPA17/PGMD5/AD0PA18/PGMD6/AD1PA21/PGMD9VDDCOREPA19/PGMD7/AD2PA22/PGMD10PA23/PGMD11PA20/PGMD8/AD3
Table 2. AT91SAM7S256 Pinout in 64-lead LQFP Package
17181920212223242526272829303132
GNDVDDIOPA16/PGMD4PA15/PGMD3PA14/PGMD2PA13/PGMD1PA24/PGMD12VDDCOREPA25/PGMD13PA26/PGMD14PA12/PGMD0PA11/PGMM3PA10/PGMM2PA9/PGMM1PA8/PGMM0PA7/PGMNVALID
33343536373839404142434445464748
TDIPA6/PGMNOEPA5/PGMRDYPA4/PGMNCMDPA27/PGMD15
PA28NRSTTSTPA29PA30PA3PA2VDDIOGNDPA1/PGMEN1PA0/PGMEN0
49505152535455565758596061626364
TDOJTAGSELTMSPA31TCKVDDCOREERASEDDMDDPVDDIOVDDFLASH
GNDXOUTXIN/PGMCKPLLRCVDDPLL
7
6117AS–ATARM–20-Oct-04
Power Considerations
Power Supplies
The AT91SAM7S256 has six types of power supply pins and integrates a voltage regu-lator, allowing the device to be supplied with only one voltage. The six power supply pintypes are:•••••
VDDIN pin. It powers the voltage regulator; voltage ranges from 3.0V to 3.6V, 3.3V nominal. If the voltage regulator is not used, VDDIN should be connected to GND.VDDOUT pin. It is the output of the 1.8V voltage regulator.
VDDIO pin. It powers the I/O lines and the USB transceivers; dual voltage range is supported. Ranges from 3.0V to 3.6V, 3.3V nominal.
VDDFLASH pin. It powers a part of the Flash and is required for the Flash to operate correctly; voltage ranges from 3.0V to 3.6V, 3.3V nominal.
VDDCORE pins. They power the logic of the device; voltage ranges from 1.65V to 1.95V, 1.8V typical. It can be connected to the VDDOUT pin with decoupling
capacitor. VDDCORE is required for the device, including its embedded Flash, to operate correctly.
VDDPLL pin. It powers the oscillator and the PLL. It can be connected directly to the VDDOUT pin.
•
No separate ground pins are provided for the different power supplies. Only GND pinsare provided and should be connected as shortly as possible to the system groundplane.
Power Consumption
The AT91SAM7S256 has a static current of less than 60 µA on VDDCORE at 25°C,including the RC oscillator, the voltage regulator and the power-on reset when thebrownout detector is deactivated. Activating the brownout detector adds 20 µA staticcurrent.
The dynamic power consumption on VDDCORE is less than 50 mA at full speed whenrunning out of the Flash. Under the same conditions, the power consumption onVDDFLASH does not exceed 10 mA.
Voltage Regulator
The AT91SAM7S256 embeds a voltage regulator that is managed by the SystemController.
In Normal Mode, the voltage regulator consumes less than 100 µA static current anddraws 100 mA of output current.
The voltage regulator also has a Low-power Mode. In this mode, it consumes less than20 µA static current and draws 1 mA of output current.
Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple andavoid oscillations. The best way to achieve this is to use two capacitors in parallel: oneexternal 470 pF (or 1 nF) NPO capacitor must be connected between VDDOUT andGND as close to the chip as possible. One external 2.2 µF (or 3.3 µF) X7R capacitormust be connected between VDDOUT and GND.
Adequate input supply decoupling is mandatory for VDDIN in order to improve startupstability and reduce source voltage drop. The input decoupling capacitor should beplaced close to the chip. For example, two capacitors can be used in parallel: 100 nFNPO and 4.7 µF X7R.
8
AT91SAM7S256 Summary Preliminary
6117AS–ATARM–20-Oct-04
AT91SAM7S256 Summary Preliminary
Typical Powering Schematics
The AT91SAM7S256 supports a 3.3V single supply mode. The internal regulator inputconnected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. Figure3 shows the power schematics to be used for USB bus-powered systems.Figure 3. 3.3V System Single Power Supply Schematic
VDDFLASHPower Sourceranges VDDIOfrom 4.5V (USB) DC/DC Converterto 18VVDDIN3.3VVoltageRegulatorVDDOUTVDDCOREVDDPLL6117AS–ATARM–20-Oct-04
9
I/O Lines Considerations
JTAG Port Pins
TMS, TDI and TCK are schmitt trigger inputs. TMS and TCK are 5-V tolerant, TDI is not.TMS, TDI and TCK do not integrate a pull-up resistor.
TDO is an output, driven at up to VDDIO, and has no pull-up resistor.
The pin JTAGSEL is used to select the JTAG boundary scan when asserted at a highlevel. The pin JTAGSEL integrates a permanent pull-down resistor of about 15 kΩ toGND, so that it can be left unconnected for normal operations.
Test Pin
The pin TST is used for manufacturing test or fast programming mode of theAT91SAM7S256 when asserted high. The pin TST integrates a permanent pull-downresistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. To enter fast programming mode, the pin TST and the pins PA0 and PA1 should be tiedhigh.
Driving the pin TST at a high level while PA0 or PA1 is driven at 0 leads to unpredictableresults.
Reset Pin
The pin NRST is bidirectional. It is handled by the on-chip reset controller and can bedriven low to provide a reset signal to the external components or asserted low exter-nally to reset the microcontroller. There is no constraint on the length of the reset pulse,and the reset controller can guarantee a minimum pulse length. This allows connectionof a simple push-button on the pin NRST as system user reset, and the use of the signalNRST to reset all the components of the system.
The pin NRST integrates a permanent pull-up resistor to VDDIO.
ERASE Pin
The pin ERASE is used to re-initialize the Flash content and some of its NVM bits. Itintegrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be leftunconnected for normal operations.
All the I/O lines PA0 to PA31 are 5V-tolerant and all integrate a programmable pull-upresistor. Programming of this pull-up resistor is performed independently for each I/Oline through the PIO controllers.
5V-tolerant means that the I/O lines can drive voltage level according to VDDIO, but canbe driven with a voltage of up to 5.5V. However, driving an I/O line with a voltage overVDDIO while the programmable pull-up resistor is enabled can lead to unpredictableresults. Care should be taken, in particular at reset, as all the I/O lines default to inputwith pull-up resistor enabled at reset.
PIO Controller A Lines
I/O Line Drive Levels
The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines candrive up to 16 mA permanently.
The remaining I/O lines (PA4 to PA31) can draw only 8 mA.
However, the total current drawn by all the I/O lines cannot exceed 150 mA.
10
AT91SAM7S256 Summary Preliminary
6117AS–ATARM–20-Oct-04
AT91SAM7S256 Summary Preliminary
Processor and Architecture
ARM7TDMI Processor
••
RISC processor based on ARMv4T Von Neumann architecture–––•
–––
Runs at up to 55 MHz, providing 0.9 MIPS/MHzARM® high-performance 32-bit instruction setThumb® high code density 16-bit instruction setInstruction Fetch (F)Instruction Decode (D)Execute(E)Two instruction sets
Three-stage pipeline architecture
Debug and Test Features•
Integrated embedded in-circuit emulator–––
Two watchpoint units
Test access port accessible through a JTAG protocolDebug communication channel
•
Debug Unit
–Two-pinUART––
Debug communication channel interrupt handlingChip ID Register
•
IEEE1149.1 JTAG Boundary-scan on all digital pins
Bus Arbiter –
Handles requests from the ARM7TDMI and the Peripheral Data ControllerThree internal 1 Mbyte memory areasOne 256 Mbyte embedded peripheral area
Source, Type and all parameters of the access leading to an abort are savedFacilitates debug by detection of bad pointersAlignment checking of all data accessesAbort generation in case of misalignment
Remaps the SRAM in place of the embedded non-volatile memoryAllows handling of dynamic exception vectors
Embedded Flash interface, up to three programmable wait states
Prefetch buffer, bufferizing and anticipating the 16-bit requests, reducing therequired wait states
Key-protected program, erase and lock/unlock sequencerSingle command for erasing, programming and locking operationsInterrupt generation in case of forbidden operationAddress decoder provides selection signals for––
Memory Controller
••
•Abort Status Registers––
•Misalignment Detector––
•Remap Command––
•Embedded Flash Controller–––––
11
6117AS–ATARM–20-Oct-04
Peripheral Data Controller
••
Handles data transfer between peripherals and memoriesEleven channels–––––
Two for each USARTTwo for the Debug Unit
Two for the Serial Synchronous ControllerTwo for the Serial Peripheral InterfaceOne for the Analog-to-digital Converter
One Master Clock cycle needed for a transfer from memory to peripheralTwo Master Clock cycles needed for a transfer from peripheral to memory
•Low bus arbitration overhead––
•Next Pointer management for reducing interrupt latency requirements
12
AT91SAM7S256 Summary Preliminary
6117AS–ATARM–20-Oct-04
AT91SAM7S256 Summary Preliminary
Memory
•
256 Kbytes of Flash Memory––––––––•
–
1024 pages of 256 bytes
Fast access time, 30 MHz single-cycle access in Worst Case conditionsPage programming time: 4 ms, including page auto-erasePage programming without auto-erase: 2 msFull chip erase time: 10 ms
10,000 write cycles, 10-year data retention capability16 lock bits, each protecting 16 sectors of 64 pagesProtection Mode to secure contents of the FlashSingle-cycle access at full speed
64 Kbytes of Fast SRAM
Memory Mapping
Internal SRAM
The AT91SAM7S256 embeds a high-speed 64-Kbyte SRAM bank. After reset and untilthe Remap Command is performed, the SRAM is only accessible at address 0x00200000. After Remap, the SRAM also becomes available at address 0x0.
The AT91SAM7S256 features one bank of 256 Kbytes of Flash. At any time, the Flashis mapped to address 0x0010 0000. It is also accessible at address 0x0 after the resetand before the Remap Command.Figure 4. Internal Memory Mapping
0x0000 00000x0010 00000x000F FFFFInternal Flash
Flash Before RemapSRAM After RemapInternal Flash1 M Bytes0x0020 0000256M Bytes0x001F FFFF1 M BytesInternal SRAM0x002F FFFF0x0030 00001 M BytesUndefined Areas(Abort)253 M Bytes0x0FFF FFFF13
6117AS–ATARM–20-Oct-04
Embedded Flash
Flash Overview
The Flash of the AT91SAM7S256 is organized in 1024 pages of 256 bytes. The 262,144bytes are organized in 32-bit words.
The Flash contains a 256-byte write buffer, accessible through a 32-bit interface.The Flash benefits from the integration of a power reset cell and from the brownoutdetector. This prevents code corruption during power supply changes, even in the worstconditions.
Embedded Flash Controller
The Embedded Flash Controller (EFC) manages accesses performed by the masters ofthe system. It enables reading the Flash and writing the write buffer. It also contains aUser Interface, mapped within the Memory Controller on the APB. The User Interfaceallows:•••••
programming of the access parameters of the Flash (number of wait states, timings, etc.)starting commands such as full erase, page erase, page program, NVM bit set, NVM bit clear, etc.
getting the end status of the last commandgetting error status
programming interrupts on the end of the last commands or on errors
The Embedded Flash Controller also provides a dual 32-bit Prefetch Buffer that opti-mizes 16-bit access to the Flash. This is particularly efficient when the processor isrunning in Thumb mode.
Lock Regions
The Embedded Flash Controller manages 16 lock bits to protect 16 regions of the flashagainst inadvertent flash erasing or programming commands. The AT91SAM7S256contains 16 lock regions and each lock region contains 64 pages of 256 bytes. Eachlock region has a size of 16 Kbytes.
If a locked-regions erase or program command occurs, the command is aborted and theEFC trigs an interrupt.
The 16 NVM bits are software programmable through the EFC User Interface. The com-mand \"Set Lock Bit\" enables the protection. The command \"Clear Lock Bit\" unlocks thelock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
Security Bit Feature
The AT91SAM7S256 features a security bit, based on a specific NVM-Bit. When thesecurity is enabled, any access to the Flash, either through the ICE interface or throughthe Fast Flash Programming Interface, is forbidden. This ensures the confidentiality ofthe code programmed in the Flash.
This security bit can only be enabled, through the Command \"Set Security Bit\" of theEFC User Interface. Disabling the security bit can only be achieved by asserting theERASE pin at 1, and after a full flash erase is performed. When the security bit is deac-tivated, all accesses to the flash are permitted.
It is important to note that the assertion of the ERASE pin should always be longer than50 ms.
As the ERASE pin integrates a permanent pull-down, it can be left unconnected duringnormal operation. However, it is safer to connect it directly to GND for the finalapplication.
14
AT91SAM7S256 Summary Preliminary
6117AS–ATARM–20-Oct-04
AT91SAM7S256 Summary Preliminary
Non-volatile Brownout Detector Control
Two general purpose NVM (GPNVM) bits are used for controlling the brownout detector(BOD), so that even after a power loss, the brownout detector operations remain in theirstate.
These two GPNVM bits can be cleared or set respectively through the commands\"Clear General-purpose NVM Bit\" and \"Set General-purpose NVM Bit\" of the EFC UserInterface.•
GPNVM Bit 0 is used as a brownout detector enable bit. Setting the GPNVM Bit 0 enables the BOD, clearing it disables the BOD. Asserting ERASE clears the GPNVM Bit 0 and thus disables the brownout detector by default.
The GPNVM Bit 1 is used as a brownout reset enable signal for the reset controller. Setting the GPNVM Bit 1 enables the brownout reset when a brownout is detected, Clearing the GPNVM Bit 1 disables the brownout reset. Asserting ERASE disables the brownout reset by default.
•
Calibration Bits
Eight NVM bits are used to calibrate the brownout detector and the voltage regulator.These bits are factory configured and cannot be changed by the user. The ERASE pinhas no effect on the calibration bits.
Fast Flash Programming The Fast Flash Programming Interface allows programming the device through either a
serial JTAG interface or through a multiplexed fully-handshaked parallel port. It allowsInterface
gang-programming with market-standard industrial programmers.
The FFPI supports read, page program, page erase, full erase, lock, unlock and protectcommands.
The Fast Flash Programming Interface is enabled and the Fast Programming Mode isentered when the TST pin and the PA0 and PA1 pins are all tied high.
The Flash of the AT91SAM7S256 is organized in 1024 pages of 256 bytes. It reads as65,536 32-bit words.
The Flash contains a 256-byte write buffer, accessible through a 32-bit interface.
15
6117AS–ATARM–20-Oct-04
System Controller
The System Controller manages all vital blocks of the microcontroller: interrupts, clocks,power, time, debug and reset.
Figure 5. System Controller Block Diagram
System Controllerjtag_nresetBoundary Scan TAP Controllerirq0-irq1fiqperiph_irq[2..14]nirqAdvanced Interrupt Controllerintnfiqproc_nresetPCKdebugARM7TDMIpit_irqrtt_irqwdt_irqdbgu_irqpmc_irqrstc_irqice_nresetforce_ntrstMCKperiph_nresetdbgu_rxdMCKdebugperiph_nresetSLCKperiph_nresetSLCKdebugidleproc_nresetcalgpnvm[0]engpnvm[1]flash_wrdisice_nresetjtag_nresetDebug Unitdbgu_irqforce_ntrstdbgu_txdsecurity_bitPeriodic Interval TimerReal-Time TimerWatchdog Timerwdt_faultWDRPROCbod_rst_enpit_irqrtt_irqflash_poeflash_wrdiscalEmbeddedFlashwdt_irqgpnvm[0..1]MCKproc_nresetBODMemory ControllerPORflash_poeReset Controllerperiph_nresetproc_nresetNRSTSLCKrstc_irqVoltage RegulatorModeControllerstandbyVoltage RegulatorcalRCOSCXINXOUTSLCKperiph_clk[2..14]pck[0-2]UDPCKperiph_clk[11]periph_nresetperiph_irq[11]usb_suspendOSCMAINCKPower ManagementControllerPCKUDPCKMCKUSB DevicePortPLLRCPLLPLLCKpmc_irqintperiph_nresetusb_suspendidleperiph_clk[4..14]periph_nresetperiph_nresetperiph_clk[2]dbgu_rxdperiph_irq{2]irq0-irq1EmbeddedPeripheralsPIO Controllerfiqdbgu_txdperiph_irq[4..14]PA0-PA31inoutenable16
AT91SAM7S256 Summary Preliminary
6117AS–ATARM–20-Oct-04
AT91SAM7S256 Summary Preliminary
System Controller Mapping
The System Controller peripherals are all mapped to the highest 4 Kbytes of addressspace, between addresses 0xFFFF F000 and 0xFFFF FFFF.
Figure 6 shows the mapping of the System Controller. Note that the Memory Controllerconfiguration user interface is also mapped within this address space.
Figure 6. System Controller Mapping
AddressPeripheralPeripheral Name0xFFFF F000AICAdvanced Interrupt Controller0xFFFF F1FF0xFFFF F200DBGUDebug Unit0xFFFF F3FF0xFFFF F400PIOAPIO Controller A0xFFFF F5FF0xFFFF F600Reserved0xFFFF FBFF0xFFFF FC00PMCPower Management Controller0xFFFF FCFF0xFFFF FD000xFFFF FD0FRSTCReset ControllerReserved0xFFFF FD200xFFFF FC2FRTTReal-time Timer 0xFFFF FD30PITPeriodic Interval Timer 0xFFFF FD400xFFFF FC3F0xFFFF FD4FWDTWatchdog Timer Reserved0xFFFF FD60VREGVoltage Regulator Mode Controller0xFFFF FD700xFFFF FC6F0xFFFF FEFFReserved0xFFFF FF00MCMemory Controller0xFFFF FFFF6117AS–ATARM–20-Oct-04
Size512 Bytes/128 registers512 Bytes/128 registers512 Bytes/128 registers256 Bytes/64 registers16 Bytes/4 registers16 Bytes/4 registers16 Bytes/4 registers16 Bytes/4 registers4 Bytes/1 register256 Bytes/64 registers17
Reset Controller
The Reset Controller is based on a power-on reset cell and one brownout detector. Itgives the status of the last reset, indicating whether it is a power-up reset, a softwarereset, a user reset, a watchdog reset or a brownout reset. In addition, it controls theinternal resets and the NRST pin output. It allows to shape a signal on the NRST line,guaranteeing that the length of the pulse meets any requirement.
The AT91SAM7S256 embeds a brownout detection circuit and a power-on reset cell.Both are supplied with and monitor VDDCORE. Both signals are provided to the Flashto prevent any code corruption during power-up or power-down sequences or if brown-outs occur on the VDDCORE power supply.
The power-on reset cell has a limited-accuracy threshold at around 1.5V. Its outputremains low during power-up until VDDCORE goes over this voltage level. This signalgoes to the reset controller and allows a full re-initialization of the device.
The brownout detector monitors the VDDCORE level during operation by comparing itto a fixed trigger level. It secures system operations in the most difficult environmentsand prevents code corruption in case of brownout on the VDDCORE.
Only VDDCORE is monitored, as a voltage drop on VDDFLASH or any other powersupply of the device cannot affect the Flash.
When the brownout detector is enabled and VDDCORE decreases to a value below thetrigger level (Vbot-, defined as Vbot - hyst/2), the brownout output is immediatelyactivated.
When VDDCORE increases above the trigger level (Vbot+, defined as Vbot + hyst/2),the reset is released. The brownout detector only detects a drop if the voltage onVDDCORE stays below the threshold voltage for longer than about 1µs.
The threshold voltage has a hysteresis of about 50 mV, to ensure spike free brownoutdetection. The typical value of the brownout detector threshold is 1.68V with an accu-racy of ± 2% and is factory calibrated.
The brownout detector is low-power, as it consumes less than 20 µA static current.However, it can be deactivated to save its static current. In this case, it consumes lessthan 1µA. The deactivation is configured through the GPNVM bit 0 of the Flash.
Brownout Detector and Power-on Reset
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Clock Generator
The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator andone PLL with the following characteristics:•RC Oscillator ranges between 22 KHz and 42 KHz•Main Oscillator frequency ranges between 3 and 20 MHz•Main Oscillator can be bypassed
•
PLL output ranges between 80 and 200 MHz
It provides SLCK, MAINCK and PLLCK.Figure 7. Clock Generator Block Diagram
Clock GeneratorEmbedded RCSlow Clock OscillatorSLCKXINMain Main ClockOscillatorMAINCKXOUTPLL and PLL ClockPLLRCDividerPLLCKStatusControlPower Management Controller6117AS–ATARM–20-Oct-04
19
Power Management Controller
The Power Management Controller uses the Clock Generator outputs to provide:•••••
the Processor Clock PCKthe Master Clock MCKthe USB Clock UDPCK
all the peripheral clocks, independently controllablethree programmable clock outputs
The Master Clock (MCK) is programmable from a few hundred Hz to the maximumoperating frequency of the device.
The Processor Clock (PCK) switches off when entering processor idle mode, thus allow-ing reduced power consumption while waiting for an interrupt.Figure 8. Power Management Controller Block Diagram
Processor Clock Controller Idle ModePCKintMaster Clock Controller SLCKMAINCKPLLCKPrescaler/1,/2,/4,...,/64MCK PeripheralsClock ControllerON/OFFperiph_clk[2..14]Programmable Clock Controller SLCKMAINCKPLLCKPrescaler/1,/2,/4,...,/64pck[0..2]USB Clock ControllerON/OFFPLLCKDivider/1,/2,/4usb_suspendUDPCKAdvanced Interrupt Controller
••
Controls the interrupt lines (nIRQ and nFIQ) of an ARM ProcessorIndividually maskable and vectored interrupt sources–––––
Source 0 is reserved for the Fast Interrupt Input (FIQ)
Source 1 is reserved for system peripherals (RTT, PIT, EFC, PMC, DBGU,etc.)
Other sources control the peripheral interrupts or external interruptsProgrammable edge-triggered or level-sensitive internal sources
Programmable positive/negative edge-triggered or high/low level-sensitiveexternal sources
Drives the normal interrupt of the processorHandles priority of the interrupt sources
Higher priority interrupts can be served during service of lower priorityinterrupt
•8-level Priority Controller–––
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•
Vectoring–––•••
–––
Optimizes interrupt service routine branch and executionOne 32-bit vector register per interrupt source
Interrupt vector register reads the corresponding current interrupt vectorEasy debugging by preventing automatic operations Permits redirecting any interrupt source on the fast interrupt
Provides processor synchronization on events without triggering an interrupt
ProtectModeFastForcing
General Interrupt Mask
Debug Unit
•Comprises:––––
One two-pin UART
One Interface for the Debug Communication Channel (DCC) supportOne set of Chip ID Registers
One Interface providing ICE Access PreventionImplemented features are compatible with the USART
Programmable Baud Rate GeneratorParity, Framing and Overrun Error
Automatic Echo, Local Loopback and Remote Loopback Channel ModesOffers visibility of COMMRX and COMMTX signals from the ARM Processor
•Two-pinUART––––
••
Debug Communication Channel Support–
Chip ID Registers
– Identification of the device revision, sizes of the embedded memories, set of–
peripherals
Chip ID is 0x270d0940 (VERSION 0)
Periodic Interval TimerWatchdog Timer
••••
20-bit programmable counter plus 12-bit interval counter
12-bit key-protected Programmable Counter running on prescaled SLCKProvides reset or interrupt signals to the system
Counter may be stopped while the processor is in debug state or in idle mode32-bit free-running counter with alarm running on prescaled SLCKProgrammable 16-bit prescaler for SLCK accuracy compensationOne PIO Controller, controlling 32 I/O linesFully programmable through set/clear registersMultiplexing of two peripheral functions per I/O line
For each I/O line (whether assigned to a peripheral or used as general-purpose I/O)–––
Input change interruptHalf a clock period glitch filter
Multi-drive option enables driving in open drain
Real-time TimerPIO Controller
••••••
21
6117AS–ATARM–20-Oct-04
––•
Programmable pull-up on each I/O line
Pin data status register, supplies visibility of the level on the pin at any time
Synchronous output, provides Set and Clear of several I/O lines in a single write
Voltage Regulator Controller
The aim of this controller is to select the Power Mode of the Voltage Regulator betweenNormal Mode (bit 0 is cleared) or Standby Mode (bit 0 is set).
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Peripherals
Peripheral Mapping
Each peripheral is allocated 16 Kbytes of address space.Figure 9. User Peripheral Mapping
0xF000 0000Reserved0xFFFA 00000xFFF9 FFFFTC0, TC1, TC20xFFFA 3FFF0xFFFA 4000Reserved0xFFFB 00000xFFFA FFFFUDP0xFFFB 3FFF0xFFFB 4000Reserved0xFFFB 80000xFFFB 7FFFTWI0xFFFB BFFF0xFFFB C000Reserved0xFFFC 00000xFFFB FFFFUSART00xFFFC 40000xFFFC 3FFFUSART10xFFFC 7FFF0xFFFC 8000Reserved0xFFFC C0000xFFFC BFFFPWMC0xFFFC FFFF0xFFFD 0000Reserved0xFFFD 40000xFFFD 3FFFSSC0xFFFD 80000xFFFD 7FFFADC0xFFFD BFFF0xFFFD C000Reserved0xFFFE 00000xFFFD FFFFSPI0xFFFE 3FFF0xFFFE 4000Reserved0xFFFE FFFF6117AS–ATARM–20-Oct-04
Peripheral NameTimer/Counter 0, 1 and 2USB Device PortTwo-Wire InterfaceUniversal Synchronous Asynchronous Receiver Transmitter 0Universal Synchronous Asynchronous Receiver Transmitter 1PWM ControllerSerial Synchronous ControllerAnalog-to-Digital ConverterSerial Peripheral InterfaceSize16 Kbytes16 Kbytes16 Kbytes16 Kbytes16 Kbytes16 Kbytes16 Kbytes16 Kbytes16 Kbytes23
Peripheral Multiplexing on PIO Lines
The AT91SAM7S256 features one PIO controller, PIOA, that multiplexes the I/O lines ofthe peripheral set.
PIO Controller A controls 32 lines. Each line can be assigned to one of two peripheralfunctions, A or B. Some of them can also be multiplexed with the analog inputs of theADC Controller.
Table 3 on page 25 defines how the I/O lines of the peripherals A, B or the analog inputsare multiplexed on the PIO Controller A. The two columns “Function” and “Comments”have been inserted for the user’s own comments; they may be used to track how pinsare defined in an application.
Note that some peripheral functions that are output only may be duplicated in the table.All pins reset in their Parallel I/O lines function are configured in input with the program-mable pull-up enabled, so that the device is maintained in a static state as soon as areset is detected.
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PIO Controller A Multiplexing
Table 3. Multiplexing on PIO Controller A PIO Controller AI/O LinePA0PA1PA2PA3PA4PA5PA6PA7PA8PA9PA10PA11PA12PA13PA14PA15PA16PA17PA18PA19PA20PA21PA22PA23PA24PA25PA26PA27PA28PA29PA30PA31Peripheral APWM0PWM1PWM2TWDTWCKRXD0TXD0RTS0CTS0DRXDDTXDNPCS0MISOMOSISPCKTFTKTDRDRKRFRXD1TXD1SCK1RTS1CTS1DCD1DTR1DSR1RI1IRQ1NPCS1Peripheral BTIOA0TIOB0SCK0NPCS3TCLK0NPCS3PCK0PWM3ADTRGNPCS1NPCS2PWM0PWM1PWM2PWM3TIOA1TIOB1PCK1PCK2FIQIRQ0PCK1NPCS3PWM0PWM1PWM2TIOA2TIOB2TCLK1TCLK2NPCS2PCK2AD0AD1AD2AD3CommentsHigh-DriveHigh-DriveHigh-DriveHigh-DriveFunctionApplication UsageComments25
6117AS–ATARM–20-Oct-04
Peripheral Identifiers
The AT91SAM7S256 embeds a wide range of peripherals. Table 4 defines the Periph-eral Identifiers of the AT91SAM7S256. A peripheral identifier is required for the controlof the peripheral interrupt with the Advanced Interrupt Controller and for the control ofthe peripheral clock with the Power Management Controller. Table 4. Peripheral Identifiers
PeripheralID0123456789101112131415 - 293031
PeripheralMnemonicAICSYSIRQ(1)PIOAReservedADC(1)SPIUS0US1SSCTWIPWMCUDPTC0TC1TC2ReservedAICAIC
Advanced Interrupt ControllerAdvanced Interrupt Controller
IRQ0IRQ1
Analog-to Digital Converter Serial Peripheral Interface USART 0USART 1
Synchronous Serial Controller Two-wire InterfacePWM ControllerUSB Device PortTimer/Counter 0Timer/Counter 1Timer/Counter 2PeripheralName
Advanced Interrupt ControllerSystem Interrupt Parallel I/O Controller A
ExternalInterruptFIQ
Note:
1.Setting SYSIRQ and ADC bits in the clock set/clear registers of the PMC has no
effect. The System Controller is continuously clocked. The ADC clock is automaticallystarted for the first conversion. In Sleep Mode the ADC clock is automatically stoppedafter each conversion.
Serial Peripheral Interface
•Supports communication with external serial devices––––
Four chip selects with external decoder allow communication with up to 15peripherals
Serial memories, such as DataFlash® and 3-wire EEPROMs
Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllersand Sensors
External co-processors
8- to 16-bit programmable data length per chip selectProgrammable phase and polarity per chip select
Programmable transfer delays between consecutive transfers and betweenclock and data per chip select
Programmable delay between consecutive transfers
•Master or slave serial peripheral bus interface––––
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––
Selectable mode fault detection
Maximum frequency at up to Master Clock
Two-wire Interface
••••
Master Mode only
Compatibility with standard two-wire serial memoriesOne, two or three bytes for slave addressSequential read/write operationsProgrammable Baud Rate Generator
5- to 9-bit full-duplex synchronous or asynchronous serial communications–––––––––––
1, 1.5 or 2 stop bits in Asynchronous Mode 1 or 2 stop bits in Synchronous ModeParity generation and error detection
Framing error detection, overrun error detectionMSB or LSB first
Optional break generation and detectionBy 8 or by 16 over-sampling receiver frequencyHardware handshaking RTS - CTS
Modem Signals Management DTR-DSR-DCD-RI on USART1Receiver time-out and transmitter timeguard
Multi-drop Mode with address generation and detection
USART
••
••••
RS485 with driver control signal
ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards–––
NACK handling, error counter with repetition and iteration limitCommunication at up to 115.2 Kbps
Remote Loopback, Local Loopback, Automatic EchoIrDA modulation and demodulationTest Modes
Serial Synchronous Controller
•••••
Provides serial synchronous communication links used in audio and telecom applications
Contains an independent receiver and transmitter and a common clock dividerOffers a configurable frame sync and data length
Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal
Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal
Three 16-bit Timer Counter Channels–
Three output compare or two input captureFrequency measurementEvent countingInterval measurementWide range of functions including:–––
Timer Counter
••
27
6117AS–ATARM–20-Oct-04
––––•
––
Pulse generationDelay timing
Pulse Width ModulationUp/down capabilitiesThree external clock inputs
Five internal clock inputs, as defined in Table 5
Each channel is user-configurable and contains:
Table 5. Timer Counter Clocks Assignment
TC Clock InputTIMER_CLOCK1TIMER_CLOCK2TIMER_CLOCK3TIMER_CLOCK4TIMER_CLOCK5
ClockMCK/2MCK/8MCK/32MCK/128MCK/1024
––
Two multi-purpose input/output signals
Two global registers that act on all three TC channels
PWM Controller
••
Four channels, one 16-bit counter per channel
Common clock generator, providing thirteen different clocks––
One Modulo n counter providing eleven clocks
Two independent linear dividers working on modulo n counter outputsIndependent enable/disable commandsIndependent clock selection
Independent period and duty cycle, with double bufferizationProgrammable selection of the output waveform polarity Programmable center or left aligned output waveform
•Independent channel programming–––––
USB Device Port
••••
USB V2.0 full-speed compliant,12 Mbits per second.Embedded USB V2.0 full-speed transceiverEmbedded 328-byte dual-port RAM for endpointsFour endpoints ––––
Endpoint 0: 8 bytes
Endpoint 1 and 2: 64 bytes ping-pongEndpoint 3: 64 bytes
Ping-pong Mode (two memory banks) for bulk endpoints
•Suspend/resume logic8-channel ADC
10-bit 100 Ksamples/sec. Successive Approximation Register ADC-2/+2 LSB Integral Non Linearity, -1/+2 LSB Differential Non LinearityIntegrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs
Analog-to-digital Converter
••••
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•••
External voltage reference for better accuracy on low voltage inputsIndividual enable and disable of each channelMultiple trigger source–––•
–Hardware or software triggerExternal trigger pin
Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger
Automatic wakeup on trigger and back to sleep mode after conversions of allSleep Mode and conversion sequencer
enabled channels
•
Four of eight analog inputs shared with digital signals
6117AS–ATARM–20-Oct-04
29
Ordering Information
Table 6. Ordering Information
Ordering CodeAT91SAM7S256-AI
PackageLQFP 64
Temperature Operating RangeIndustrial(-40°C to 85°C)
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Document Details
Title
AT91SAM7S256Literature Number
6117S
Revision History
Version A
Publication Date: 20-Oct-04
6117AS–ATARM–20-Oct-04
31
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