CHIP-PACKAGING WITH BONDING OPTIONS CONNECTED TO A

专利名称：CHIP-PACKAGING WITH BONDING

OPTIONS CONNECTED TO A PACKAGESUBSTRATE

发明人：Cheng-Yen Huang申请号：US11854558申请日：20070913

公开号：US20080003714A1公开日：20080103

专利附图：

摘要：A chip-packaging includes a package substrate, a chip, and a lead frame. Thechip having a plurality of bonding pads is mounted on the package substrate. One of

these bonding pads is connected to the package substrate. The package substrate has aGND voltage or a POWER voltage. The lead frame is connected to one bonding pad. Withconnection of these bonding pads with the lead frame and connection of these bondingpads with the package substrate, input ends or output ends in the chip could beconnected to a GND voltage, a POWER voltage, and signal pins of the chip-packaging.

申请人：Cheng-Yen Huang

地址：Hsin-Chu City TW

国籍：TW

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