STM706T/S/R, STM706P, STM708T/S/R
3V Supervisor
FEATURES SUMMARY
■
■■■■■■■■
PRECISION VCC MONITOR–STM706/708
T: 3.00V ≤ VRST ≤ 3.15VS: 2.88V ≤ VRST ≤ 3.00V
R; STM706P: 2.59V ≤ VRST ≤ 2.70VRST AND RST OUTPUTS200ms (TYP) trec
WATCHDOG TIMER - 1.6sec (TYP)MANUAL RESET INPUT (MR)
POWER-FAIL COMPARATOR (PFI/PFO)LOW SUPPLY CURRENT - 40µA (TYP)GUARANTEED RST (RST) ASSERTION DOWN TO VCC = 1.0V
OPERATING TEMPERATURE:–40°C to 85°C (Industrial Grade)
Figure 1. Packages81SO8 (M)TSSOP8 3x3 (DS)Table 1. Device Options
Watchdog Input
STM706T/S/RSTM706P(2)STM708T/S/R
✔✔
Watchdog Output
✔✔
✔Active-Low RST(1)
✔
✔✔Active-High RST(1)
Manual Reset Input
✔✔✔
Power-fail Comparator
✔✔✔
Note:1.Push-Pull Output
2.The STM706P is identical to the STM706R, except its reset output is active-high.
February 20051/26
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STM706T/S/R; STM706P; STM708T/S/R
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 1.Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Table 1.Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 2.Logic Diagram (STM706T/S/R and STM706P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 3.Logic Diagram (STM708T/S/R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Table 2.Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 4.STM706T/S/R and STM706P SO8 Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Figure 5.STM706T/S/R and STM706P TSSOP8 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Figure 6.STM708T/S/R SO8 Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Figure 7.STM708T/S/R TSSOP8 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Table 3.Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Figure 8.Block Diagram (STM706T/S/R and STM706P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Figure 9.Block Diagram (STM708T/S/R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Figure 10.Hardware Hookup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Reset Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Push-button Reset Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Watchdog Input (STM706T/S/R and STM706P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Watchdog Output (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Power-fail Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Ensuring a Valid Reset Output Down to VCC=0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Figure 11.Reset Output Valid to Ground Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Interfacing to Microprocessors with Bi-directional Reset Pins . . . . . . . . . . . . . . . . . . . . . . . .10Figure 12.Interfacing to Microprocessors with Bi-directional Reset I/O. . . . . . . . . . . . . . . . . . . . . .10TYPICAL OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 13.Supply Current vs. Temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Figure 14.VPFI Threshold vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Figure 15.Reset Comparator Propagation Delay vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . .11Figure 16.Power-up trec vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Figure 17.Normalized Reset Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Figure 18.Watchdog Time-out Period vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Figure 19.PFI to PFO Propagation Delay vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Figure 20.Output Voltage vs. Load Current (VCC = 5V; VBAT = 2.8V; TA = 25°C). . . . . . . . . . . . . .14Figure 21.Output Voltage vs. Load Current (VCC = 0V; VBAT = 2.8V; TA = 25°C). . . . . . . . . . . . . .14Figure 22.RST Output Voltage vs. Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Figure 23.RST Output Voltage vs. Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Figure 24.Power-fail Comparator Response Time (Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Figure 25.Power-fail Comparator Response Time (De-Assertion) . . . . . . . . . . . . . . . . . . . . . . . . .16
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Figure 26.Maximum Transient Duration vs. Reset Threshold Overdrive. . . . . . . . . . . . . . . . . . . . .17MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 4.Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 5.Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Figure 27.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Figure 28.Power-fail Comparator Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Figure 29.MR Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Figure 30.Watchdog Timing (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Table 6.DC and AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 31.SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical. . . . . . .21Table 7.SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data . .21Figure 32.TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline . . . . . . . . . . .22Table 8.TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data. . . .22PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 9.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Table 10.Marking Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 11.Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
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STM706T/S/R; STM706P; STM708T/S/R
SUMMARY DESCRIPTION
The STM70x Supervisors are self-contained de-vices which provide microprocessor supervisoryfunctions. A precision voltage reference and com-parator monitors the VCC input for an out-of-toler-ance condition. When an invalid VCC conditionoccurs, the reset output (RST) is forced low (orhigh in the case of RST).
These devices also offer a watchdog timer (exceptfor STM708T/S/R) as well as a power-fail compar-ator to provide the system with an early warning ofimpending power failure.
The STM706P is identical to the STM706R, exceptits reset output is active-high.
These devices are available in a standard 8-pinSOIC package or a space-saving 8-pin TSSOPpackage.
Figure 2. Logic Diagram (STM706T/S/R and STM706P)VCCTable 2. Signal Names
MRWDIWDORSTPush-button Reset InputWatchdog InputWatchdog OutputActive-Low Reset OutputActive-High Reset OutputSupply VoltagePower-fail InputPower-fail OutputGroundNo Connect
WDIMRPFISTM706T/S/R,STM706PWDORST (RST)PFO(1)RST(1)VCCPFIPFOVSSAI08841VSSNC
Note:1.For STM706P only.
Note:1.For STM706P and STM708T/S/R only.
Figure 3. Logic Diagram (STM708T/S/R)VCCRSTMRSTM708T/S/RPFIRSTPFOVSSAI088424/26
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Figure 4. STM706T/S/R and STM706P SO8 ConnectionsSO8MRVCCVSSPFI12348765WDORST(RST)(1)WDIPFOAI08837Figure 6. STM708T/S/R SO8 ConnectionsSO8MRVCCVSSPFI12348765RSTRSTNCPFOAI08839Note:1.For STM706P reset output is active-high.
Figure 5. STM706T/S/R and STM706P TSSOP8 ConnectionsTSSOP8RST(RST)(1)Figure 7. STM708T/S/R TSSOP8 ConnectionsTSSOP8WDOMRVCC12348765WDIPFOPFIVSSAI08838RSTRSTMRVCC12348765NCPFOPFIVSSAI08840Note:1.For STM706P reset output is active-high.
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Pin Descriptions
RST.Pulses low for trec when triggered, and staysMR.A logic low on MR asserts the reset output.Reset remains asserted as long as MR is low andlow whenever VCC is below the reset threshold orfor trec after MR returns high. This active-low inputwhen MR is a logic low. It remains low for trec afterhas an internal pull-up. It can be driven from a TTLeither VCC rises above the reset threshold, the
watchdog triggers a reset, or MR goes from low toor CMOS logic line, or shorted to ground with a high.switch. Leave open if unused.
RST.Pulses high for trec when triggered, andWDI.If WDI remains high or low for 1.6sec, the in- stays high whenever Vternal watchdog timer runs out and reset (or WDO)CC is above the reset
is triggered. The internal watchdog timer clearsthreshold or when MR is a logic high. It remains after either VCC falls below the resethigh for twhile reset is asserted or when WDI sees a risingrec
threshold, the watchdog triggers a reset, or MRor falling edge.
goes from high to low.The watchdog function cannot be disabled by al- PFI.When PFI is less than VPFI, PFO goes low;lowing the WDI pin to float.
otherwise, PFO remains high. Connect to groundWDO.WDO goes low when a transition does notif unused.occur on WDI within 1.6sec, and remains low until
a transition occurs on WDI (indicating the watch-PFO.When PFI is less than VPFI, PFO goes low;otherwise, PFO remains high. Leave open if un-dog interrupt has been serviced). WDO also goeslow when VCC falls below the reset threshold; how-used.
ever, unlike the reset output, WDO goes high assoon as VCC exceeds the reset threshold.
Note: For those devices with a WDO output, awatchdog timeout will not trigger reset unlessWDO is connected to MR.Table 3. Pin Description
Pin
STM706P
STM706T/S/R
STM708T/S/R
Name
Function
SO8TSSOP8SO8TSSOP8SO8TSSOP8168–72453–
382–14675–
1687–2453–
3821–4675–
1––7824536
3––1246758
MRWDIWDORSTRSTVCCPFIPFOVSSNC
Push-button Reset InputWatchdogInputWatchdog OutputActive-Low Reset OutputActive-HighResetOutputSupply VoltagePFIPower-failInputPFO Power-fail OutputGroundNoConnect
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Figure 8. Block Diagram (STM706T/S/R and STM706P)WDIWDITransitionalDetectorWATCHDOGTIMERWDOVCCVCCVRSTCOMPAREMRtrecGeneratorRST(RST)(1)PFIVPFICOMPAREPFOAI08829Note:1.For STM706P only.
Figure 9. Block Diagram (STM708T/S/R)VCCVRSTCOMPARERSTVCCtrecGeneratorRSTMRPFIVPFICOMPAREPFOAI088307/26
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STM706T/S/R; STM706P; STM708T/S/R
Figure 10. Hardware HookupRegulatorVINVCCVCCUnregulatedVoltage0.1µFSTM706T/S/R;STM706P;STM708T/S/RWDIR1From MicroprocessorPFIR2Push-buttonMR(1)WDO(1)PFORSTRST(2)To Microprocessor IRQTo Microprocessor NMITo Microprocessor ResetAI08843Note:1.For STM706T/S/R and STM706P.
2.For STM706P and STM708T/S/R.
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OPERATION
Reset Output
The STM70x Supervisor asserts a reset signal tothe MCU whenever VCC goes below the resetthreshold (VRST), a watchdog time-out occurs (ifWDO is connected to MR), or when the Push-but-ton Reset Input (MR) is taken low. RST is guaran-teed to be a logic low (logic high for STM706P andSTM708T/S/R) for VCC < VRST down to VCC =1Vfor TA = 0°C to 85°C.
During power-up, once VCC exceeds the resetthreshold an internal timer keeps RST low for thereset time-out period, trec. After this interval RSTreturns high.
If VCC drops below the reset threshold, RST goeslow. Each time RST is asserted, it stays low for atleast the reset time-out period (trec). Any time VCCgoes below the reset threshold the internal timerclears. The reset timer starts when VCC returnsabove the reset threshold.Push-button Reset Input
A logic low on MR asserts reset. Reset remainsasserted while MR is low, and for trec (see Figure29.,page19) after it returns high. The MR inputhas an internal 40kΩ pull-up resistor, allowing it tobe left open if not used. This input can be drivenwith TTL/CMOS-logic levels or with open-drain/collector outputs. Connect a normally open mo-mentary switch from MR to GND to create a man-ual reset function; external debounce circuitry isnot required. If MR is driven from long cables orthe device is used in a noisy environment, connecta 0.1µF capacitor from MR to GND to provide ad-ditional noise immunity. MR may float, or be tied toVCC when not used.
Watchdog Input (STM706T/S/R and STM706P)The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not toggle theWatchdog Input (WDI) within tWD (1.6sec), theWatchdog Output pin (WDO) is asserted. The in-ternal 1.6sec timer is cleared by either:1.a reset pulse, or
2.by toggling WDI (high-to-low or low-to-high),
which can detect pulses as short as 50ns.See Figure 30.,page19 for STM706T/S/R andSTM706P.
The timer remains cleared and does not count foras long as reset is asserted. As soon as reset is re-leased, the timer starts counting.
Watchdog Output (STM706T/S/R and STM706P)
When VCC drops below the reset threshold, WDOwill go low even if the watchdog timer has not yettimed out. However, unlike the reset output, WDOgoes high as soon as VCC exceeds the resetthreshold. WDO may be used to generate a resetpulse by connecting it to the MR input.Power-fail Input/Output
The Power-fail Input (PFI) is compared to an inter-nal reference voltage (independent from the VRSTcomparator). If PFI is less than the power-failthreshold (VPFI), the Power-Fail Output (PFO) willgo low. This function is intended for use as an un-dervoltage detector to signal a failing power sup-ply. Typically PFI is connected through an externalvoltage divider (see Figure 10.,page8) to eitherthe unregulated DC input (if it is available) or theregulated output of the VCC regulator. The voltagedivider can be set up such that the voltage at PFIfalls below VPFI several milliseconds before theregulated VCC input to the STM70x or the micro-processor drops below the minimum operatingvoltage.
If the comparator is unused, PFI should be con-nected to VSS and PFO left unconnected. PFOmay be connected to MR on the STM70x so that alow voltage on PFI will generate a reset output.Ensuring a Valid Reset Output Down to VCC=0V
When VCC falls below 1V, the state of the RST out-put can no longer be guaranteed, and becomesessentially an open circuit. If a high value pull-down resistor is added to the RST pin, the outputwill be held low during this condition. A resistor val-ue of approximately 100kΩ will be large enough tonot load the output under operating conditions, butstill sufficient to pull RST to ground during this lowvoltage condition (see Figure 11).
Figure 11. Reset Output Valid to Ground CircuitSTM70xRSTR1AI088449/26
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Interfacing to Microprocessors with Bi-directional Reset Pins
Microprocessors with bi-directional reset pins cancontend with the STM70x reset output. For exam-ple, if the reset output is driven high and the microwants to pull it low, signal contention will result. Toprevent this from occurring, connect a 4.7kΩ resis-tor between the reset output and the micro’s resetI/O as in Figure 12.
Figure 12. Interfacing to Microprocessors with Bi-directional Reset I/OBuffered Reset to otherSystem ComponentsVCCSTM70x4.7kRSTRSTVCCMicroprocessorGNDGNDAI08845TYPICAL OPERATING CHARACTERISTICS
Note: Typical values are at TA = 25°C.
Figure 13. Supply Current vs. Temperature (no load)3025Supply Current (µA)2015VCC = 2.7VVCC = 3.0VVCC = 3.6VVCC = 4.5VVCC = 5.5V1050–40–20020406080100120AI09141bTemperature (°C)10/26
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Figure 14. VPFI Threshold vs. Temperature1.2701.2651.260VCC = 2.5VVCC = 3.0VVCC = 3.3VVCC = 3.6VVPFI Threshold (V)1.2551.2501.2451.2401.2351.2301.225–40–20020406080100120AI09142bTemperature (°C)Figure 15. Reset Comparator Propagation Delay vs. Temperature302826Propagation Delay (µs)2422201816141210–40–20020406080100120AI09143bTemperature (°C)11/26
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Figure 16. Power-up trec vs. Temperature240235230trec (ms)VCC = 3.0V225VCC = 4.5VVCC = 5.5V220215210–40–20020406080100120AI09144bTemperature (°C)Figure 17. Normalized Reset Threshold vs. Temperature1.004Normalized Reset Threshold1.0021.0000.9980.996–40–20020406080100120AI09145bTemperature (°C)12/26
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Figure 18. Watchdog Time-out Period vs. Temperature1.90Watchdog Time-out Period (sec)1.851.801.75VCC = 3.0VVCC = 4.5VVCC = 5.5V1.701.651.60–40–20020406080100120AI09146bTemperature (°C)Figure 19. PFI to PFO Propagation Delay vs. Temperature4.0PFI to PFO Propagation Delay (µs)VCC = 3.0V3.0VCC = 3.6VVCC = 4.5VVCC = 5.5V2.01.00.0–40–20020406080100120AI09148bTemperature (°C)13/26
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Figure 20. Output Voltage vs. Load Current (VCC = 5V; VBAT = 2.8V; TA = 25°C)5.004.98VOUT (V)4.964.9401020304050AI10496IOUT (mA)Figure 21. Output Voltage vs. Load Current (VCC = 0V; VBAT = 2.8V; TA = 25°C)2.802.782.76VOUT (V)2.742.722.702.682.660.00.20.40.60.81.0AI10497IOUT (mA)14/26
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Figure 22. RST Output Voltage vs. Supply Voltage5VRSTVCC544VRST (V)221100500ms/divAI09149bFigure 23. RST Output Voltage vs. Supply Voltage5VRSTVCC544VRST (V) 22110500ms/div0AI09150b15/26
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STM706T/S/R; STM706P; STM708T/S/R
Figure 24. Power-fail Comparator Response Time (Assertion)5VPFO1V/div0V1.3VPFI500mV/div0V500ns/divAI09153bFigure 25. Power-fail Comparator Response Time (De-Assertion)5VPFO1V/div0V1.3VPFI500mV/div0V500ns/divAI09154b16/26
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Figure 26. Maximum Transient Duration vs. Reset Threshold Overdrive60005000Transient Duration (µs)4000Reset occursabove the curve.30002000100000.0010.010.1110AI09156bReset Comparator Overdrive, VRST – VCC (V)MAXIMUM RATING
Stressing the device above the rating listed in theAbsolute Maximum Ratings” table may cause per-manent damage to the device. These are stressratings only and operation of the device at these orany other conditions above those indicated in theOperating sections of this specification is not im-Table 4. Absolute Maximum Ratings
SymbolTSTGTSLD(1)VIOVCCIOPD
Parameter
Storage Temperature (VCC Off)
Lead Solder Temperature for 10 secondsInput or Output VoltageSupply VoltageOutput CurrentPower Dissipation
Value–55 to 150
260–0.3 to VCC +0.3–0.3 to 7.0
20320
Unit°C°CVVmAmW
plied. Exposure to Absolute Maximum Rating con-ditions for extended periods may affect devicereliability. Refer also to the STMicroelectronicsSURE Program and other relevant quality docu-ments.
Note:1.Reflow at peak temperature of 255°C to 260°C for < 30 seconds (total thermal budget not to exceed 180°C for between 90 to 150
seconds).
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DC AND AC PARAMETERS
This section summarizes the operating measure-ment conditions, and the DC and AC characteris-tics of the device. The parameters in the DC andAC characteristics Tables that follow, are derivedfrom tests performed under the Measurement
Conditions summarized in Table 5, Operating andAC Measurement Conditions. Designers shouldcheck that the operating conditions in their circuitmatch the operating conditions when relying onthe quoted parameters.
Table 5. Operating and AC Measurement Conditions
Parameter
VCC Supply Voltage
Ambient Operating Temperature (TA)Input Rise and Fall TimesInput Pulse Voltages
Input and Output Timing Ref. Voltages
STM70x1.0 to 5.5–40 to 85≤50.2 to 0.8VCC0.3 to 0.7VCC
UnitV°CnsVV
Figure 27. AC Testing Input/Output Waveforms0.8VCC0.7VCC0.3VCCAI025680.2VCC
Figure 28. Power-fail Comparator WaveformVCCVRSTtrecPFORSTAI08860a18/26
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STM706T/S/R; STM706P; STM708T/S/R
Figure 29. MR Timing WaveformMRtMLRLRST (1)tMLMHtrecAI07837aNote:1.RST for STM706P and STM708T/S/R.
Figure 30. Watchdog Timing (STM706T/S/R and STM706P)VCCRSTtrecWDItWDWDOAI08833Table 6. DC and AC Characteristics
SymVCCICC
Alter-native
Description
Operating VoltageVCC Supply Current
Input Leakage Current (WDI)
ILI
Input Leakage Current (PFI)Input Leakage Current (MR)VCC < 3.6VVCC < 5.5V0V = VIN = VCC0V = VIN = VCCVRST (max) < VCC < 3.6V
4.5V < VCC < 5.5V4.5V < VCC < 5.5VVRST (max) < VCC < 3.6VVRST (max) < VCC < 5.5V
4.5V < VCC < 5.5VVRST (max) < VCC < 3.6VVRST (max) < VCC < 5.5V
–1–2525752.00.7VCC0.7VCC
0.80.60.3VCC
280125
Test Condition(1)
Min1.2(2)
3540Typ
Max5.55060+1+25250300
UnitVµAµAµAnAµAµAVVVVVV
VIHVIHVILVIL
Input High Voltage (MR)Input High Voltage (WDI)Input Low Voltage (MR)Input Low Voltage (WDI)
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SymVOL
Alter-native
Description
Output Low Voltage (PFO, RST, RST, WDO)Test Condition(1)VCC = VRST (max),ISINK = 3.2mAISINK = 50µA, VCC = 1.0V,
TA = 0°C to 85°CISINK = 100µA, VCC = 1.2V
Output High Voltage (RST, RST, WDO)Output High Voltage (PFO)Power-fail ComparatorVPFItPFD
PFI Input ThresholdPFI to PFO Propagation DelayPFI Falling
(STM70xP/R, VCC = 3.0V; STM70xS/T, VCC = 3.3V)
1.20
1.252
1.30
Vµs
ISOURCE = 1mA,VCC = VRST (max)ISOURCE = 75µA,VCC = VRST (max)
2.40.8VCCMin
Typ
Max0.30.30.3
UnitVVVVV
VOLOutput Low Voltage (RST)VOH
Reset Thresholds
STM706P/70xR
VRST
Reset Threshold(3)
STM70xSSTM70xT
Reset Threshold Hysteresis
trec
RST Pulse Width1402.552.853.00
2.632.933.0820200
2802.703.003.15
VVVmVms
Push-button Reset InputtMLMH
tMR
MR Pulse WidthVRST (max) < VCC < 3.6V
4.5V < VCC < 5.5VVRST (max) < VCC < 3.6V
4.5V < VCC < 5.5V
500150
750250
nsnsnsns
tMLRLtMRDMR to RST Output DelayWatchdog Timer (STM706T/S/R and STM706P)
STM706P/70xR,VCC = 3.0VSTM70xS/70XT,VCC = 3.3V4.5V < VCC < 5.5VVRST (max) < VCC < 3.6V
tWDWatchdog Timeout Period1.121.602.24s
WDI Pulse Width
50100
nsns
Note:1.Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = VRST (max) to 5.5V (except where noted).
2.VCC (min) = 1.0V for TA = 0°C to +85°C.3.For VCC falling.
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PACKAGE MECHANICAL
Figure 31. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanicalh x 45˚A2BeDACddd8E1HA1αLSO-ANote:Drawing is not to scale.
Table 7. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
SymbAA1BCDdddEeHhLαN
mm
Typ–––––––1.27––––
Min1.350.100.330.194.80–3.80–5.800.250.400°8
Max1.750.250.510.255.000.104.00–6.200.500.908°
Typ–––––––0.050––––
inches Min0.0530.0040.0130.0070.189–0.150–0.2280.0100.0160°8
Max0.0690.0100.0200.0100.1970.0040.157–0.2440.0200.0358°
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Figure 32. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, OutlineD85E1Ec14αA1ACPbeA2LL1TSSOP8BMNote:Drawing is not to scale.Table 8. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data
SymbAA1A2bcCPDeEE1LL1αN
mm
Typ––0.85–––3.000.654.903.000.550.95–
Min–0.050.750.250.13–2.90–4.652.900.40–0°8
Max1.100.150.950.400.230.103.10–5.153.100.70–6°
Typ––0.034–––0.1180.0260.1930.1180.0220.037–
inches Min–0.0020.0300.0100.005–0.114–0.1830.1140.016–0°8
Max0.0430.0060.0370.0160.0090.0040.122–0.2030.1220.030–6°
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PART NUMBERING
Table 9. Ordering Information Scheme
Example:
STM706
T
M
6
E
Device TypeSTM706STM708
Reset Threshold VoltageT: 3.00V ≤ VRST ≤ 3.15VS: 2.88V ≤ VRST ≤ 3.00V
R, STM706P: 2.59V ≤ VRST ≤ 2.70V
PackageM = SO8DS = TSSOP8
Temperature Range6 = –40 to 85°C
Shipping MethodE = TubesF = Tape & Reel
For other options, or for more information on any aspect of this device, please contact the ST Sales Officenearest you.
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Table 10. Marking Description
Part NumberSTM706P
Reset Threshold
2.63V
PackageSO8TSSOP8SO8TSSOP8SO8TSSOP8SO8TSSOP8SO8TSSOP8SO8TSSOP8SO8TSSOP8
Topside Marking
706P
STM706T3.08V706T
STM706S2.93V706S
STM706R2.63V706R
STM708T3.08V708T
STM708S2.93V708S
STM708R2.63V708R
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REVISION HISTORY
Table 11. Document Revision History
DateOctober 200312-Dec-0316-Jan-0409-Apr-0425-May-0402-Jul-0421-Sep-0425-Feb-05
Version1.02.02.13.04.05.06.07.0
First Issue
Reformatted; update characteristics (Figure 2, 3, 8, 9, 10, 28, 29, 30; Table 6, 7, 8, 9)
Add Typical Operating Characteristics (Figure 13, 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26)
Reformatted; update characteristics (Figure 15, 19, 22, 23, 26; Table 6)Update characteristics (Table 3, 6)
Datasheet promoted; waveform corrected (Figure 28)
Clarify root part numbers; (Figure 2, 3, 4, 5, 6, 7, 8, 9, 10, 30; Table 1, 3, 6, 9)Update Typical Characteristics (Figure 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
Revision Details
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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